1. Technical Field
The area of each cell of a memory such as a DRAM is increasingly reduced due to refinement of a fine processing technology and a cell structure. Implementation of a large-capacity semiconductor memory device thereby becomes possible. It has been proposed that, in the DRAM (dynamic random access memory) using 4F2 cells in particular, the area of each DRAM cell is reduced by using a three-dimensional structure. In this three-dimensional structure, a pillar-shaped projection is provided on a semiconductor substrate surface, a cell capacitance is connected to the top of the pillar-shaped projection, and the pillar-shaped projection is connected to a buried bit line provided on the foot of the pillar projection, through a cell transistor provided on a sidewall of the pillar-shaped projection.
Patent Document 1 describes a semiconductor integrated circuit which aims at improvement of a static noise margin characteristic. This semiconductor integrated circuit includes flip-flop type memory cells of an SRAM or the like. A pull-down circuit is provided for the semiconductor integrated circuit, for reducing a voltage of a word line to a supply voltage or less when the word line is active. The pull-down circuit is provided to prevent the voltage of the word line from excessively increasing, thereby aiming at improvement of the static noise margin characteristic.
[Patent Document 1]    JP Patent Kokai Publication No. JP2008-262637A, which corresponds to US Patent Application Publication No. 2008/0253172A1.